libcpuid
libcpuid_arm_driver.h
1/*
2 * Copyright 2024 Veselin Georgiev,
3 * anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#ifndef __LIBCPUID_ARM_DRIVER_H__
28#define __LIBCPUID_ARM_DRIVER_H__
29
30#define AARCH64_REG_MIDR_EL1 "S3_0_C0_C0_0"
31#define AARCH64_REG_MPIDR_EL1 "S3_0_C0_C0_5"
32#define AARCH64_REG_REVIDR_EL1 "S3_0_C0_C0_6"
33#define AARCH64_REG_ID_AFR0 "S3_0_C0_C1_3"
34#define AARCH64_REG_ID_DFR0 "S3_0_C0_C1_2"
35#define AARCH64_REG_ID_DFR1 "S3_0_C0_C3_5"
36#define AARCH64_REG_ID_ISAR0 "S3_0_C0_C2_0"
37#define AARCH64_REG_ID_ISAR1 "S3_0_C0_C2_1"
38#define AARCH64_REG_ID_ISAR2 "S3_0_C0_C2_2"
39#define AARCH64_REG_ID_ISAR3 "S3_0_C0_C2_3"
40#define AARCH64_REG_ID_ISAR4 "S3_0_C0_C2_4"
41#define AARCH64_REG_ID_ISAR5 "S3_0_C0_C2_5"
42#define AARCH64_REG_ID_ISAR6 "S3_0_C0_C2_7"
43#define AARCH64_REG_ID_MMFR0 "S3_0_C0_C1_4"
44#define AARCH64_REG_ID_MMFR1 "S3_0_C0_C1_5"
45#define AARCH64_REG_ID_MMFR2 "S3_0_C0_C1_6"
46#define AARCH64_REG_ID_MMFR3 "S3_0_C0_C1_7"
47#define AARCH64_REG_ID_MMFR4 "S3_0_C0_C2_6"
48#define AARCH64_REG_ID_MMFR5 "S3_0_C0_C3_6"
49#define AARCH64_REG_ID_PFR0 "S3_0_C0_C1_0"
50#define AARCH64_REG_ID_PFR1 "S3_0_C0_C1_1"
51#define AARCH64_REG_ID_PFR2 "S3_0_C0_C3_4"
52#define AARCH64_REG_ID_AA64AFR0_EL1 "S3_0_C0_C5_4"
53#define AARCH64_REG_ID_AA64AFR1_EL1 "S3_0_C0_C5_5"
54#define AARCH64_REG_ID_AA64DFR0_EL1 "S3_0_C0_C5_0"
55#define AARCH64_REG_ID_AA64DFR1_EL1 "S3_0_C0_C5_1"
56#define AARCH64_REG_ID_AA64DFR2_EL1 "S3_0_C0_C5_2"
57#define AARCH64_REG_ID_AA64FPFR0_EL1 "S3_0_C0_C4_7"
58#define AARCH64_REG_ID_AA64ISAR0_EL1 "S3_0_C0_C6_0"
59#define AARCH64_REG_ID_AA64ISAR1_EL1 "S3_0_C0_C6_1"
60#define AARCH64_REG_ID_AA64ISAR2_EL1 "S3_0_C0_C6_2"
61#define AARCH64_REG_ID_AA64ISAR3_EL1 "S3_0_C0_C6_3"
62#define AARCH64_REG_ID_AA64MMFR0_EL1 "S3_0_C0_C7_0"
63#define AARCH64_REG_ID_AA64MMFR1_EL1 "S3_0_C0_C7_1"
64#define AARCH64_REG_ID_AA64MMFR2_EL1 "S3_0_C0_C7_2"
65#define AARCH64_REG_ID_AA64MMFR3_EL1 "S3_0_C0_C7_3"
66#define AARCH64_REG_ID_AA64MMFR4_EL1 "S3_0_C0_C7_4"
67#define AARCH64_REG_ID_AA64PFR0_EL1 "S3_0_C0_C4_0"
68#define AARCH64_REG_ID_AA64PFR1_EL1 "S3_0_C0_C4_1"
69#define AARCH64_REG_ID_AA64PFR2_EL1 "S3_0_C0_C4_2"
70#define AARCH64_REG_ID_AA64SMFR0_EL1 "S3_0_C0_C4_5"
71#define AARCH64_REG_ID_AA64ZFR0_EL1 "S3_0_C0_C4_4"
72
73typedef enum {
74 REQ_MIDR,
75 REQ_MPIDR,
76 REQ_REVIDR,
77 REQ_ID_AFR0,
78 REQ_ID_DFR0,
79 REQ_ID_DFR1,
80 REQ_ID_ISAR0,
81 REQ_ID_ISAR1,
82 REQ_ID_ISAR2,
83 REQ_ID_ISAR3,
84 REQ_ID_ISAR4,
85 REQ_ID_ISAR5,
86 REQ_ID_ISAR6,
87 REQ_ID_MMFR0,
88 REQ_ID_MMFR1,
89 REQ_ID_MMFR2,
90 REQ_ID_MMFR3,
91 REQ_ID_MMFR4,
92 REQ_ID_MMFR5,
93 REQ_ID_PFR0,
94 REQ_ID_PFR1,
95 REQ_ID_PFR2,
96#if defined(__aarch64__)
97 REQ_ID_AA64AFR0,
98 REQ_ID_AA64AFR1,
99 REQ_ID_AA64DFR0,
100 REQ_ID_AA64DFR1,
101 REQ_ID_AA64DFR2,
102 REQ_ID_AA64FPFR0,
103 REQ_ID_AA64ISAR0,
104 REQ_ID_AA64ISAR1,
105 REQ_ID_AA64ISAR2,
106 REQ_ID_AA64ISAR3,
107 REQ_ID_AA64MMFR0,
108 REQ_ID_AA64MMFR1,
109 REQ_ID_AA64MMFR2,
110 REQ_ID_AA64MMFR3,
111 REQ_ID_AA64MMFR4,
112 REQ_ID_AA64PFR0,
113 REQ_ID_AA64PFR1,
114 REQ_ID_AA64PFR2,
115 REQ_ID_AA64SMFR0,
116 REQ_ID_AA64ZFR0,
117#endif /* __aarch64__ */
118 /* termination: */
119 NUM_REG_REQUESTS,
120 REQ_INVALID = -1
121} reg_request_t;
122
123struct read_reg_t {
124 reg_request_t request;
125 union {
126 uint32_t value_32b;
127 uint64_t value_64b;
128 };
129};
130typedef struct read_reg_t read_reg_t;
131
132#define ARM_IOC_READ_REG _IOWR('c', 0xB0, read_reg_t)
133
134#endif /* __LIBCPUID_ARM_DRIVER_H__ */
read_reg_t
Definition libcpuid_arm_driver.h:123
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